1. Field of the Invention
The present invention relates to a differential amplifier, and more particularly to a linear transconductance amplifier having a linear transconductance formed on a semiconductor integrated circuit.
2. Description of Related Art
Conventionally, this kind of a CMOS linear transconductance amplifier, such as a circuit shown in FIG. 7 of the publication; IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL-CAS32,NO.11, NOVEMBER 1985, PP.1097-1103, xe2x80x9cCMOS Voltage to Current Transducersxe2x80x9d, realizes a linear operation by executing a subtraction of the drain currents of the two MOS transistors M1 and M2 having the square-law characteristic with respect to the input voltage. This scheme is well known, and an operation of the circuit having such an output circuit arrangement is referred to as a class AB operation.
Neglecting an effect depending of a substrate and an influence of channel length modulation, and assuming that the relation between the drain current and the gate-source voltage of a MOS transistor operating in a saturation region obeys the square-law, the drain current of the MOS transistor is expressed as follows:
xe2x80x83ID=xcex2(VGSxe2x88x92VTH)2(VGSxe2x89xa7VTH)xe2x80x83xe2x80x83(1a)
ID=0(VGSxe2x89xa6VTH)xe2x80x83xe2x80x83(1b)
where xcex2=xcexc(Cox/2)(W/L) is a transconductance parameter, xcexcis an effective mobility of carrier, COX is a gate oxide film capacity per unit area, W and L are a gate width and a gate length, respectively, and VTH is a threshold voltage.
Referring to the left of FIG. 7, there is a relationship as follows:
Vln=VGS1+VGS2xe2x88x92[VGS3+VGS4]xe2x80x83xe2x80x83(2)xe2x80x2
Equation (2)xe2x80x2 can be reduces to the following equation (2).
Vin=VGSeqxe2x88x92(Vb+VTHeq)xe2x80x83xe2x80x83(2)
Here, if a CMOS-pair consisting of an N-channel MOS transistor and a P-channel MOS transistor is regarded as one complex transistor, VGSeq, xcex2eq, and VTHeq are expressed as follows:                               V          GSeq                =                              V            THeq                    +                                    1                                                β                  eq                                                      ⁢                                          2                ⁢                I                                                                        (        3        )                                          β          eq                =                                            β              N                        ⁢                          β              P                                                          (                                                                    β                    N                                                  +                                                      β                    P                                                              )                        2                                              (        4        )                                          V          THeq                =                              V            THN                    +                      V            THP                                              (        5        )            
In addition, Vb is expressed as follows:
Vb={square root over (2I/xcex2eq)}xe2x80x83xe2x80x83(6)
From equation (3) the following equation (7) is obtained:                               V          in                =                                                            2                ⁢                                  I                  1                                                            β                eq                                              -                      V            b                                              (        7        )            
Referring to the left of FIG. 7, the current I1 is expressed as follows                               I          1                =                                            β              eq                        2                    ⁢                                    (                                                V                  b                                +                                  V                  in                                            )                        2                                              (        8        )            
Similarly, referring to the right of FIG. 7, the current I2 is expressed as follows:                               I          2                =                                            β              eq                        2                    ⁢                                    (                                                V                  b                                -                                  V                  in                                            )                        2                                              (        9        )            
Consequently, the output current is expressed as follows:
Vout=I1xe2x88x92I2=2xcex2eqVbVin=2{square root over (2xcex2eqIbVin)}xe2x80x83xe2x80x83(10)
FIG 8 is a graph for explaining a linear operation. The input voltage has a linear region as follows:
xe2x88x92{square root over (2Ib/xcex2eq)} less than Vin less than {square root over (2Ib/xcex2eq)}xe2x80x83xe2x80x83(11)
The output current has a linear region as follows:
xe2x88x924b less than Iout less than 4Ibxe2x80x83xe2x80x83(12)
Essentially, the circuit shown in FIG. 7 is a multiplier core circuit capable of implementing a multiplier circuit in itself, which is based on the following identity (13) providing a multiplying function.                                           1            4                    ⁢                      {                                                            (                                      x                    +                    y                                    )                                2                            -                                                (                                      x                    +                    y                                    )                                2                                      }                          =                  x          ⁢                      xe2x80x83                    ⁢          y                                    (        13        )            
This technique including the value of the coefficient is referred to as xe2x80x9cThe quarter-square techniquexe2x80x9d and widely known. Accordingly, the scheme involving the subtraction of the outputs of the square-circuit is regarded as the only linearization scheme. Furthermore, the inventor considers that the scheme in which a two-quadrant multiplier is used as a linear transconductance amplifier is not sophisticated in terms of circuit arrangement, the two-quadrant multiplier being configured by fixing one input side of the multiplier core circuit with a linear transconductance capable of implementing a four-quadrant operation to restrict the same to a two-quadrant operation.
However, since the conventional CMOS linear transconductance amplifier has the P-channel MOS transistor in the signal line for subtraction of the output currents, it is difficult to improve a frequency characteristic thereof.
In analog signal processings, a differential amplifier is an essential function block. Particularly, a requirement of a MOS differential amplifier with a linear characteristic has been grown. Thus, an object of the present invention is to provide a linear transconductance amplifier which is easily implemented with LSI and superior in a frequency characteristic.
According to a first aspect of the present invention, there is provided a linear transconductance amplifier in which gates of a first and second transistors having their sources grounded are connected to each other to constitute an input terminal pair. The linear transconductance amplifier comprises means for forming an added current by adding two currents substantially equal to the drain currents of the first and second transistors, respectively, a constant current source for outputting a constant current, and means for forming a subtracted current by subtracting the addition current from the constant current. In the linear transconductance amplifier, one differential output current is formed by adding the drain current of the first transistor and a current almost a half of the subtraction current, and the other differential output current is formed by adding the drain current of the second transistor and a current almost a half of the subtraction current. Further, an input voltage applied to the input terminal pair is a differential voltage superimposed on a constant DC voltage (claim 1). Transistor described here includes a MOS (metal-oxide semiconductor) transistor, a MIS (metal insulator semiconductor) transistor, and the like.
More particularly, the first linear transconductance amplifier according to the present invention has the following configuration (claim 2). There is provided a linear transconductance amplifier comprising a first, second, third and fourth N-channel MOS transistor""s having their sources grounded, a constant current source for outputting a constant current, and a current mirror circuit in which a ratio between an input current and an output current is constant. In the linear transconductance amplifier, gates of the first and third MOS transistors are connected to each other to constitute one terminal of an input terminal pair, and gates of the second and fourth MOS transistors are connected to each other to constitute the other terminal of the input terminal pair. The constant current is separated into two currents, one of which is the sum of drain currents of the third and fourth MOS transistors and the other of which is an input current of the current mirror circuit. Furthermore, the sum of a drain current of the first MOS transistor and an output current of the current mirror circuit constitutes one differential output current, and the sum of a drain current of the second MOS transistor and an output current of the current mirror circuit constitutes the other differential output current.
In the second liner transconductance amplifier according to the present invention, gates of a first and second transistors having their sources grounded are connected to each other, and further connected to the drains of the first and second transistors through resistors, respectively, and gates of a third and fourth transistors having their sources grounded are connected to the drains of the first and second transistors, thereby constituting an input terminal pair. The linear transconductance amplifier comprises means for forming an added current by adding two currents substantially equal to drain currents of the third and fourth transistors, respectively, a constant current source for outputting a constant current, and means for forming a subtracted current by subtracting the addition current from the constant current. In the linear transconductance amplifier, one differential output current is formed by adding the drain current of the first transistor to a current almost a half of the subtraction current, and the other differential output current is formed by adding the drain current of the second transistor to a current almost a half of the subtraction current, and an input current applied to the input terminal pair is a differential current superimposed on a constant DC current (claim 3).
More particularly, the second linear transconductance amplifier according to the present invention has the following configuration (claim 4). The linear transconductance amplifier comprises a first, second, third, fourth, fifth and sixth N-channel MOS transistors having their sources grounded, a first and second resistors, a constant current source for outputting a constant current, and a current mirror circuit in which a ratio between an input current and an output current is constant. Gates of said third and fifth MOS transistors are connected to each other to constitute one terminal of an input terminal pair, and gates of the fourth and sixth MOS transistors are connected to each other to constitute the other terminal of the input terminal pair. Further, the first and second resistors are connected in series between one terminal of the input terminal pair and the other terminal of the input terminal pair, and a drain of the first MOS transistor is connected to one terminal of the input terminal pair and a gate of the first MOS transistor is connected to a connection point between the first and second resistors, and a drain of the second MOS transistor is connected to the other terminal of the input terminal pair and a gate of the second MOS transistor is connected to the connection point between the first and second resistors. Furthermore, the constant current is separated into two currents, one of which is the sum of drain currents of the fifth and sixth MOS transistors and the other of which is an input current of the current mirror circuit. Moreover, one differential output current is formed by the sum of a drain current of the third MOS transistor and an output current of the current mirror circuit, and the other differential output current is formed by the sum of a drain current of the fourth MOS transistor and the output current of the current mirror circuit.
The third liner transconductance amplifier according to the present invention, in which gates of a first and second transistors having their sources grounded constitute an input terminal pair, comprises means for forming an added current by adding two currents substantially equal to a half of drain currents of the first and second transistors, respectively. One differential output current is formed by subtracting the drain current of the first transistor from the addition current, and the other differential output current is formed by subtracting the drain current of the second transistor from the addition current. Further, an input voltage applied to the input terminal pair is a differential voltage superimposed on a constant DC voltage (claim 5).
More particularly, the third linear transconductance amplifier according to the present invention has the following configuration (claim 6). The linear transconductance amplifier comprises a first, second, third, fourth, fifth and sixth N-channel MOS transistors having their sources grounded, a first current mirror circuit, and first and second current mirror circuits in which a ratio between an input current and an output current is constant. In the third linear transconductance amplifier, gates of the first, third and fifth MOS transistors are connected to each other to constitute one terminal of an input terminal pair, and gates of the second, fourth and sixth MOS transistors are connected to each other to constitute the other terminal of the input terminal pair. Further, an input current of the first current mirror circuit is separated into two currents, one of which is a drain current of the third MOS transistor and the other of which is a drain current of the fourth MOS transistor, and an input current of the second current mirror circuit is separated into two currents, one of which is a drain current of the fifth MOS transistor and the other of which is a drain current of the sixth MOS transistor. Furthermore, an output current of the first current mirror circuit is separated into two currents, one of which is a drain current of the first MOS transistor and the other of which is one differential output current, and an output current of the second current mirror circuit is separated into two currents, one of which is a drain current of the second MOS transistor and the other of which is the other differential output current.
The fourth linear transconductance amplifier according to the present invention, in which gates of a first and second transistors having their sources grounded are connected to each other and further connected to drains of the first and second transistors through resistors, respectively, and gates of a third and fourth transistors having their sources grounded are connected to the drains of the first and second transistors, thereby constituting an input terminal pair, comprises means for forming an added current by adding two currents substantially equal to a half of drain currents of the third and fourth transistors, respectively. In the forth linear transconductance amplifier, one differential output current is formed by subtracting the drain current of the third transistor from the addition current, and the other differential output current is formed by subtracting the drain current of the forth transistor from the addition current. Further, an input current applied to the input terminal pair is a differential current superimposed on a constant DC current.
More particularly, the fourth linear transconductance amplifier according to the present invention has the following configuration (claim 8). The linear transconductance amplifier comprises a first, second, third, fourth, fifth, sixth, seventh and eighth N-channel MOS transistors having their sources grounded, a first and second resisters, and a first and second current mirror circuits, in which a ratio between an input current and an output current is constant. In the forth linear transconductance amplifier, gates of the third, fifth and seventh MOS transistors are connected to each other to constitute one terminal of an input terminal pair, and gates of the fourth, sixth and eighth MOS transistors are connected to each other to constitute the other terminal of the input terminal pair. Further, the first and second resistors are connected in series between one terminal of the input terminal pair and the other terminal of the input terminal pair. Furthermore, a drain of the first MOS transistor is connected to one terminal of the input terminal pair Land a gate of the first MOS transistor is connected to a connection point between the first and second resistors, and a drain of the second MOS transistor is connected to the other terminal of the input terminal pair and a gate of the second MOS transistor is connected to the connection point between the first and second resistors. Moreover, an input current of the first current mirror circuit is separated into two currents, one of which is a drain current of the seventh MOS transistor and the other of which is a drain current of said eighth MOS transistor, and an input current of the second current mirror circuit is separated into two currents, one of which is a drain current of the fifth MOS transistor and the other of which is a drain current of the sixth MOS transistor. Still further, an output current of the first current mirror circuit is separated into two currents, one of which is a drain current of the third MOS transistor and the other of which is one differential output current, and an output current of the second current mirror circuit is separated into two currents, one of which is a drain current of the fourth MOS transistor and the other of which is the other differential output current.
Operations of the linear transconductance amplifier according to the present invention is as follows: the scheme for obtaining a linear characteristic from a curve with square-law characteristic, which is generally referred to as a parabolic characteristic, includes a scheme involving a way by adding a square-law characteristic to a parabolic characteristic, besides the scheme involving subtracting a parabolic characteristic from another parabolic characteristic described with regard to the conventional circuit example. If such an addition is an addition of currents, it is expected that frequency characteristic is improved in that the linear transconductance amplifier can be configured without any P-channel transistor in a signal path.